发明名称 Transmission system for the synchronous digital hierarchy
摘要 A digital transmission system having at least one adaptation circuit for compensating for phase variations of a STM-N signal. For inserting justification locations for at least one container of the STM-N signal, the adaptation circuit (8) includes a buffer (17, 51), a write address generator (16, 53), a read address generator (18, 61) a justification decision circuit (24, 60) and an output circuit (19, 62). The buffer stores container data in which justification locations may be inserted. The write address generator provides write addresses for data to be written in the buffer, and the read address generator provides read addresses in the buffer. In one embodiment differences between the read and write address values are combined with justification information which has been low pass filtered. In another embodiment these differences are low pass filtered and used for forming the justification decision signal. The output circuit inserts positive or negative justification locations in data read from the buffer to form the container.
申请公布号 US5343476(A) 申请公布日期 1994.08.30
申请号 US19930148017 申请日期 1993.11.05
申请人 U.S. PHILIPS CORPORATION 发明人 URBANSKY, RALPH
分类号 H04J3/07;H04J3/00;H04J3/06;H04L7/00;(IPC1-7):H04J3/06;H04L7/04 主分类号 H04J3/07
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