| 发明名称 |
PHASE-LOCK LOOP CIRCUIT WITH IMPROVED OUTPUT SIGNAL JITTER PERFORMANCE |
| 摘要 |
The invention provides an improved phase-lock loop circuit that exhibits an output signal jitter performance improvement of orders of magnitude. The invention comprises a method of controlling the phase-lock loop circuit by targeting on the transition zone between two sampling windows.
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| 申请公布号 |
CA2004842(C) |
申请公布日期 |
1994.08.23 |
| 申请号 |
CA19892004842 |
申请日期 |
1989.12.07 |
| 申请人 |
NORTHERN TELECOM LIMITED |
发明人 |
SYLVAIN, DANY |
| 分类号 |
H03L7/085;H03L7/183;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/085 |
| 代理机构 |
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代理人 |
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| 地址 |
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