| 摘要 |
<p>PURPOSE:To achieve operation at a wide frequency range which can also be applied to low-frequency operation. CONSTITUTION:In the decoder, input signals G1-G6 which are synchronized to a clock signal C1 are input to gates. decoder output wires O1-O4 are precharged to a first potential by the clock signal C1, N-channel MOS transistors 111-115, 121-125, 131-136, and 141-145 are selectively activated by a clock signal C2, decoder output wires O1-O4 are selectively set to a second potential, and then the potential of the decoder output wires O1-O4 is latched by a clock signal C2. The title decoder is provided with a P-channel MOS transistor 25 which is activated by the clock signal C2 and a means for controlling the latch signal for latching the potential of the decoder output wires O1-O4 by receiving the control signal output from the MOS transistor 25.</p> |
