发明名称 Cache tag parity detect circuit
摘要 A memory which is cleared by simultaneously clearing a special bit in each entry within the memory, an extra bit, used for other purposes, is also cleared. When both bits have a value of 0, parity checking is disabled. When either bit has a value of 1, parity checking is enabled. This prevents incorrect detection of parity errors after the memory device has been cleared.
申请公布号 US5339322(A) 申请公布日期 1994.08.16
申请号 US19910677313 申请日期 1991.03.29
申请人 SGS-THOMSON MICROELECTRONICS, INC. 发明人 RASTEGAR, BAHADOR
分类号 G06F11/10;G06F12/08;G06F12/16;(IPC1-7):G06F11/10 主分类号 G06F11/10
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