Full swing power down buffer circuit with multiple power supply isolation

摘要

A full swing CMOS output buffer circuit (20,30,40,50) isolates incompatible power supply circuits such as 3.3 v standard and 5 v standard subcircuits, and isolates power supply rails of quiet or powered down buffer circuits from the common external bus. The pullup output transistor (PMOS1) is fabricated in a well (NWELL) of N type carrier semiconductor material formed in a substrate (PSUB) of P type carrier semiconductor material. A P channel NWELL isolation switch transistor (PW1) has a primary current path coupled between the well (NWELL) and high potential power rail (VCC) and a control gate node coupled to the control gate node of the pullup output transistor (PMOS1) for operating substantially in phase. The NWELL isolation switch transistor (PW1) isolates the pullup output transistor (PMOS1) well (NWELL) from the high potential power rail (VCC). An N channel control node isolation transistor (N1) has a control node coupled to the high potential power rail (VCC) for isolating the control nodes of the output transistors (PMOS1,NMOS1) from each other during power down. A P channel feedback turn off transistor (PP1) has a control node coupled to the high potential power rail (VCC) for turning off the output transistor (PMOS1) in response to a higher potential level signal at the output (VOUT). A delay discharge circuit (DDC) discharges transient charge from the high potential power rail (VCC) during power down.