| 摘要 |
PURPOSE:To suppress the errors of + or -1 bit in code conversion data due to noise or the like by adding '1' at the time of the decrease of data by a comparator circuit. CONSTITUTION:A delay circuit 1 is provided and binary linear code input data represented by the complement of '2' inputted at a certain sampling period are held for one sampling period. By the comparator circuit 2, the output of the delay circuit 1 is compared with the linear code input data and comparison signals are outputted. A complement circuit 3 is provided and the complement of '1' of the linear code input data is obtained. An exclusive OR circuit 4 is provided and the exclusive OR of the code bit of the linear code input data and the comparison signal is taken. An adding circuit 5 letting exclusive OR output be the carry input of a least significant bit is provided and the output of the complement circuit 3 is defined as input A conversion circuit 6 is provided and the output of the adding circuit 5 is converted to nonlinear PCM codes. |
