| 摘要 |
The parallel test circuit is for testing memory devices in parallel and for discriminating the test result simultaneously. The parallel test circuit includes MOS-transistors (N1-NK) having drains connected to a common I/O line (11), MOS transisters (n1-nk) having drains connected to a common I/O lines (12), transisters (P1,P2) for precharging the I/O lines (11,12) a sense amplifier (2) for generating discriminating signal by amplifying voltage level difference between the I/O lines (11,12), sense amplifiers (4,6) for amplifying voltage difference between the I/O lines and a reference voltage, and a NAND gate (8) for generating test signal by comparing output signals of the sense amplifiers (4,6).
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