发明名称 CLOCK REPRODUCING CIRCUIT FOR MSK DEMODULATOR
摘要 PURPOSE:To reproduce a clock with low C/N by extracting the secondary harmonic component of the clock by a channel filter and attenuating the main lobe component of the MSK spectrum by an LPF before phase comparison to control the phase synchronizing oscillation frequency. CONSTITUTION:The secondary harmonic component of the clock extracted from the MSK modulated wave input by a channel filter 21 is subjected to FM detection by an FM detector 22, and the main lobe component is attenuated by an LPF 23 to obtain a reference signal, The oscillation frequency which is four times as high as the clock frequency outputted from a VCXO 14 is divided into 1/2 by a 1/2 frequency divider 27, and the signal obtained by this frequency division and the reference signal are compared with each other by a phase comparator 24 to output an error signal, The frequency of the VCO 14 is controlled by this error signal, and it is operated as a phase synchronizing oscillator. The output of the filter 21 is subjected to orthogonal detection by an orthogonal detector 29, and an eye pattern is obtained from demodulated data through a waveform shaping filter 30. Thus, the jitter is reduced, and the clock is stably reproduced with low C/N.
申请公布号 JPH06216950(A) 申请公布日期 1994.08.05
申请号 JP19930007495 申请日期 1993.01.20
申请人 TOSHIBA CORP 发明人 MAEDA HIROTO
分类号 H03L7/08;H04L27/14 主分类号 H03L7/08
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