| 摘要 |
PURPOSE: To control clock signal without using any delay line. CONSTITUTION: An integrated circuit has an oscillator 18 for generating the plural phases of oscillator clock signal. The respective phases of oscillator clock respectively control one of plural ring shift registers 30, 32, 34 and 36. The outputs of respective steps of these ring shift registers are the phases of desired clock signal and also inputs to a multiplexer 38 for selectively providing one of these desired clock phases as the output of multiplexer. For the other example of execution, this ring shift register generates the half of desired clock signal phases with the multiple of desired frequency. The output of this multiplexer performs the clock control of bisecting circuit, multiplexers 46, 48, 50 and 52 at different levels are arranged at the back of this multiplexer, and the other half of these phases is generated and divided into desired frequencies. |
