| 摘要 |
PURPOSE:To provide the phase control circuit relieving positional fluctuation of an input frame pulse signal and coping with a high speed signal by easily revising a phase of the input pulse signal with small sized circuit configuration without a design change. CONSTITUTION:First-n-th delay signals F11-F1n obtained by delaying the phase of an input pulse signal F1 by 1-bit-n-bits respectively by means of 1st-n-th delay means 111-11n connected in series by N-stages through synchronization are obtained and outputted to a selection setting means 15, the means 15 selects optionally any of the signals F11-F1n to be outputted to 1st-n-th reception circuits on the rear stage, and the selected signal (such as F11) is outputted to a prescribed reception circuit at a timing requested by the 1st-n-th reception circuits on the rear stage. |
