Method and configuration for reducing electrical noise in integrated circuit devices

摘要

A chip packaging configuration prevents differential electrical coupling within a plurality of associated bit lines (14 and 16) by associating, under lead frame (26), a first packaging material having a first dielectric constant and a second packaging material having a second dielectric constant and where the first packaging material and second packaging material are configured to expose the plurality of associated bit lines (14 and 16) to allow approximately equal coupling to lead frame (26) for each bit line (14 and 16) through the first and second dielectric constant to thereby prevent differential electrical coupling of the plurality of bit lines (14 and 16) with lead frame (26).