| 摘要 |
A phase lock loop (PLL) is configured as a frequency synthesizer with a first programmable frequency divider placed in the input signal path and a second programmable frequency divider located between the output of an current controlled oscillator (ICO) and the second input of a phase detector. A charge pump receives control pulses from the phase detector to generate first and second currents to control the ICO. The control currents are low-pass filtered and summed before application to the ICO. To improve loop stability, the summation current to the ICO is duplicated and used to control the bias on the charge pump. With proper biasing, first and second control currents become dependent on the second programmable divider ratio and maintain the unity gain bandwidth of the loop constant at a value much less than the digital sampling rate.
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