发明名称 |
GRAPHIC / IMAGE PROCESSING METHOD AND DEVICE |
摘要 |
<p>PURPOSE: To easily execute parallel processing by arranging the pins of a smart video memory so that the memory can be accessed directly from an external element as a standard video memory element. CONSTITUTION: A program memory 12 is connected to an instruction decoder 14 and the decoder 14 outputs a control signal to a logic unit 16 when the decoder 14 decodes an instruction existing in the memory 12. The unit 16 is connected to the memory 12 and a data memory 18 and the memory 18 is directly connected to an access memory 19. A memory controller 20 is also connected to the unit 16. In an element 10, pins are arranged so that the element 10 can be accessed from an external element as a standard video memory element. The element 10 contains 40 pins and each pin is provided with an input and output which are equivalent to those of a representative VRAM.</p> |
申请公布号 |
JPH06208632(A) |
申请公布日期 |
1994.07.26 |
申请号 |
JP19930209696 |
申请日期 |
1993.08.24 |
申请人 |
TEXAS INSTR INC <TI> |
发明人 |
BASABARAJI AI PAWATE;BETEI PURINSU |
分类号 |
G06F12/00;G06F15/78;G06T1/60;G09G5/39;(IPC1-7):G06F15/78;G06F15/64 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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