| 摘要 |
PURPOSE:To hold the inside data even by an analog divider circuit by converting the voltage level into the time by means of the charging characteristic of an RC circuit and registering the time in a digital counter as the clock number. CONSTITUTION:The output of a multiplexer MUX which outputs alternatively the analog data D1-Dn to undergo the multiplication and division is supplied to a comparator COMP as the non-inverted input. An RC circuit RC1 is connected to the inverted input of the COMP, and a step type start signal RV1 is supplied to the circuit RC1. The COMP has output 0 when the input (Dk-RV1) is smaller than 0 and then produces the significant output 1 when (Dk-RV1)>=0 is satisfied. The output of the COMP and the signal RV1 are supplied to a logical gate G, and the output of the gate G is supplied to a counter CNT as an enable signal E. In other words, the CNT performs its counting action in a period when the signal RV1 set at 1 is supplied and then the output of the COMP is set at 1. |
