A frame phase synchronization apparatus and method and a phase synchronization apparatus for TDM frames.

摘要

A first frame counter generates a position signal for an input subframe address which is synchronized with an input clock signal based on an input frame phase signal. The first frame counter also generates a write address enabling signal. A subframe type detector generates a write/read control signal based on an input frame signal. Depending upon the position signal for the input subframe address, the write address enabling signal and the write/read control signal, a first subframe phase synchronization means and a second to nth subframe phase synchronization means control a buffer corresponding to 1/m of a frame data amount by a write address, where m (n>=m) is a multiplexing number. The first subframe phase synchronization means and the second to mth subframe phase synchronization means writes data corresponding to a first to mth input subframe signal based on the input frame signal into a buffer respectively. An input relative phase is synchronized with a standard relative phase. The synchronized signal is output as a synchronized frame signal.