| 摘要 |
An output driver circuit includes a sense amplifier coupled to a first inverter and a second inverter. The first and second inverters drive a first and second chain of logic gates, respectively. A p-channel output transistor is coupled to the output of the first chain of logic gates, and an n-channel output transistor is coupled to the output of the second chain of logic gates. The transistors in the first and second inverters are selected so that the first inverter and the second inverter have complementary preferential output states. The first and second inverters generate their preferential output state in response to a selected intermediate output voltage range from the sense amplifier to turn off both the n-channel transistor and the p-channel transistor. This causes the n-channel and p-channel output transistors to both turn off when the sense amplifier generates the intermediate voltage during an equilibrate period.
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