| 摘要 |
<p>PURPOSE:To enable clock control to be stopped at a target count value by outputting a basic signal and a delay signal during a valid period until a cycle counter outputs a stop signal corresponding to a previously decided flag. CONSTITUTION:A clock generation part 1 generates the clock of a specified cycle (t). When a starting instruction is inputted, a cycle counter 2 counts the generated clock and when the count value is turned to a specified count value, the stop signal is outputted. A control part 3 is operated by the starting instruction, decides the valid term until the cycle counter 2 outputs the stop signal corresponding to the flag previously set before the starting instruction, and outputs the basic valid period signal and the delay valid period signal. The clock is inputted to a basic cycle clock validating part 4, and the clock is outputted during the period instructed by the basic valid period signal. The clock is inputted to a t/N delay cycle clock validating part 5, validated during the period instructed by the delay valid period signal, and delayed just for a period t/N.</p> |
