发明名称 CIRCUIT FOR EXECUTING CONDITIONAL BRANCH INSTRUCTIONS IN A PIPELINED PROCESSOR
摘要 A circuit for executing conditional branch instructions in a pipeline process comprises registers for retaining condition codes settled at different stages, respectively, registers for retaining pipeline tags identifying instructions at the respective stages and indicating the stage where the condition codes are settled, and a branch controller for deciding settlement of condition codes for conditional branch instructions existing at the respective stage according to the tags in a plurality of stages, and for selecting the settled condition codes from among the condition codes stored in the registers. <IMAGE>
申请公布号 EP0497579(A3) 申请公布日期 1994.07.13
申请号 EP19920300756 申请日期 1992.01.29
申请人 FUJITSU LIMITED 发明人 ASAKAWA, TAKEO;INOUE, AIICHIRO
分类号 G06F9/32;G06F9/38 主分类号 G06F9/32
代理机构 代理人
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