| 摘要 |
A lock detection circuit (2) for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal (REFERENCE). The lock detection circuit includes a circuit for generating first (UP) and second (DOWN) pulses, the first and second pulses respectively representing positive and negative differences between a parameter, such as phase, of the PLL signal and a parameter of the reference signal, and a first counter (4) for counting sets of first and second, pulses, each set comprising a first pulse followed by a second pulse, the first counter on counting a predetermined number of sets of pulses providing a first count complete signal. The lock detection circuit further includes a second counter (6) for counting transitions of the reference signal (REFERENCE), and being coupled to the circuit for generating whereby the second counter is reset by the first (UP) or second (DOWN)pulse, the second counter (6) on counting a predetermined number of transitions of the reference signal providing a second count complete signal, and a logic circuit (20) for generating a signal (LOCK) indicating lock has been achieved in response to the receipt of either the first or second count complete signal. Preferably, the lock detection circuit further includes a pulse width detection circuit (30) for detecting the widths of the first and second pulses and in response to detecting the width of either of the first or second pulse is greater than a predetermined value for providing a reset signal which resets the first and second counter.
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