| 摘要 |
PURPOSE:To generate a reception clock with a few amount of jitter at the time of transmitting data by a pair of cables, by comparing the phase of a clock outputted from a frequency division circuit with the phase of a clock outputted from a word synchronization circuit in the established state of synchronization. CONSTITUTION:When a binary signal 100 is inputted, a phase comparator 2 decides the lead or the lag of the phase of the binary signal 100 for a reference clock 2fOA in a digital phase locking oscillator A. A digital loop filter 3 controls the oscillation frequency of a digital voltage controlled oscillator 4 corresponding to the decided result of the phase comparator 2. The frequency divider 5 generates an fOA clock and a 2fOA clock by frequency-dividing the output 104 of the voltage controlled oscillator 4. The fOA clock and the 2fOA clock are synchronized with the binary signal 100. And when the fO rises synchronizing with the binary signal 100, the reference clock to perform phase comparison at the phase comparator 2 is switched from the 2fOA to the fOA by controlling a selector 8 by the output 107b of the word synchronization circuit 7. |
