| 摘要 |
PURPOSE:To provide a contention operation verification system capable of frequently generating contention operations at asynchronous timings and further reducing the overhead of a program. CONSTITUTION:This contention operation verification system for the hardware logical verification of a computer is constituted of a central processing unit (CPU) 101, a main storage device 102, a bus controller 103, an object input/ output device 104 and a pseudo input/output device 105. The pseudo input/output device 105 is provided with the storage function 108 of data to the pseudo input/output device 105, an ejecting function 109 to the object input/output device 104 and a completion interruption output function and a DMA operation by the pseudo input/output device 105 independent front the CPU 101 and a PMA operation occupying the CPU 101 alternately performed between the object input/output device 104 and the main storage device 102 set as initial data are simultaneously executed. |
