发明名称 CLOCK CONTROL METHOD
摘要 PURPOSE:To prevent occurrence of a data error at the time of switching a system by issuing an alarm when a phase difference between inputted 0 system and 1 system clocks is more than a normal value. CONSTITUTION:The duplexed 0-system and 1-system clocks transmitted from a DCS are received, one clock is selected by a selecting circuit 31 of a selecting part 30, the clock is switched to the other clock when a disconnection abnormal fault occurs at the clock, and supplied to a phase synchronizing oscillator 60 as an in-device reference clock. This selecting part 30 is provided with a phase monitoring means 40 which inputs the 0-system and 1-system clocks, the output clock of the selector 31, and the clock outputted by the phase synchronizing oscillator 60, monitors the phase difference between the inputted 0-system and 1-system clocks, and issues an alarm at the time of detecting that the phase difference is more than the preliminarily set value. Then, the phase monitoring means 40 issues the alarm at the time of detecting that the phase difference between the 0-system and 1-system input clocks is more than the preliminarily set value.
申请公布号 JPH06177866(A) 申请公布日期 1994.06.24
申请号 JP19920329726 申请日期 1992.12.10
申请人 FUJITSU LTD 发明人 TAKAHASHI YUJI;YOSHINO TOYOHIKO
分类号 H04L1/22;G06F1/04;H04L7/00 主分类号 H04L1/22
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