| 摘要 |
PURPOSE:To prevent latchup phenomenon, by applying a voltage higher than a power supply voltage to the substrate region of a pMOS transistor, and applying a voltage lower than an earth potential to the substrate region of an nM0S transistor. CONSTITUTION:A step-up potential Vpp higher than a power supply voltage Vdd is supplied to an internal circuit block 1, from a step-up potential generating circuit 11. A voltage lower than the earth potential Vss is supplied to the block 1, from a substrate bias generating circuit 8. The step-up potential generating circuit 11 is connected also with the substrate region of a pMOS transistor 4, and supplies a step-up potential Vpp to the substrate region. The substrate bias generating circuit 8 is connected also with the substarate of an nM0S transistor 5, and supplies a potential Vdd to the substrate region. When an overshoot is generated in an output waveform, the step-up voltage Vpp higher than the power supply voltage Vdd is applied to the substrate region of the pMOS transistor 4, so that minority carrier is not injected into the substrate, and a parasitic thyristor is prevented from turning ON. |
