| 摘要 |
PURPOSE:To shorten the operation time to about 1/4 of a conventional example at the time when a parameter N of power remainder operation C CE mod N of n-bit length ((n) is an even) is expressed by product PXQ of two primes p and Q having the 1/2-bit length. CONSTITUTION:Power remainder computing elements 101 and 102 of n/2-bit length and adding/subtracting circuits 104 and 105 of n/2-bit length which are used as power remainder computing elements of n-bit length and adder/ subtractors of n-bit length also by control of respective carry signals in a CPU 107 are provided. The CPU 107 executes two power remainder operations of n/2-bit length in parallel and performs the processing before and after them to perform the power remamder operation of n-bit length. |
