Testing and repairing process for memory chips on a wafer, each chip having a redundancy circuit

摘要

Disclosed a wafer testing process of a semiconductor device provided with a redundancy circuit. The process comprises a step of removing a passivation film above a pad and link portion, a pre-laser testing, a laser-repairing, and a final quality marking of a off-line inking method. Therefore, fabrication-test processes are simplified to one step by adopting off-line inking method, thereby achieving productivity improvement, quality enhancement, and reduction of throughput time.