| 摘要 |
A temperature compensated ECL output driver circuit incorporates an ECL output gate (Q4,Q3) coupled between high (VCC) and low (VEE) potential power rails with output voltage swing resistors (R2, R1). The ECL output gate provides an output node (N1) at the collector node of one of the ECL output gate transistors (Q4). A first current sink (Q5,R4) is coupled between the common emitter node coupling (N3) of the ECL output gate (Q4,Q3) and low potential power rail (VEE). A compensating current source (Q11,R5) is coupled to the ECL output gate output node (N1) for generating a supplementary compensating current during operation of the ECL output driver circuit in intermediate and high temperature operating ranges. A compensating current switch (Q9,Q10) is coupled in the compensating current path and is constructed for switching off the supplementary compensating current in a specified low temperature operating range to maintain the logic high output signal VOH within specifications. The compensating current switch is an ECL compensating current switch (CCS) gate (Q9,Q10) and the compensating current source is a second current sink (Q11,R5) coupled to the ECL CCS gate.
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