发明名称 STEREO DEMODULATOR CIRCUIT
摘要 PURPOSE:To eliminate the effect of the signal featuring an odd-multiplication of 19kHz by providing the voltage control oscillator circiut, the phase comparator circuit with the 19kHz pilot signal and the trap featuring the frequency of an odd- multiplication to the pilot signal. CONSTITUTION:The input signal to be supplied to FM stereo demodulator circuit 7 processing other signals in the odd-multiplication frequency component (for example, 57kHz) of the pilot signal of 19kHz is supplied to switching circuit 1 as well as to phase comparator circuit 2 via 57kHz trap circuit 8. At circuit 1, both the switching-demodulated L and R signals are isolated from each other, and the signal with elimination of 57kHz is compared at circuit 2 for the phase with the signal obtained by giving 1/4 division at divider circuits 5 and 6 to the output of voltage control oscillator VCO4. This comparison output controls VCO4 via LPF3. Thus a good separation can be ensured since the signal supplied to circuit 1 is free from the phase shift up to the high range.
申请公布号 JPS5563148(A) 申请公布日期 1980.05.13
申请号 JP19780135609 申请日期 1978.11.02
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HORIIKE YOSHIO
分类号 H04B1/16;H04H40/45;H04H40/63 主分类号 H04B1/16
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