发明名称 MULTI-LAYER TOLERANCE CHECKER
摘要 Multi-layer printed circuit boards are sometimes connected to transmission paths which may be susceptible to electrical discharges associated with transient electrical events occurring along the transmission path. A method is provided for assuring that two respective layers of the printed circuit board are aligned within predetermined tolerances. Aligning respective layers within acceptable tolerances provides a means of assuring that predetermined distances between a ground layer and a power layer will be maintained, thereby ensuring that electrical arcing will not occur between the power and ground layer in the event of voltage spikes or current surges.
申请公布号 CA2017865(C) 申请公布日期 1994.06.21
申请号 CA19902017865 申请日期 1990.05.30
申请人 NORTHERN TELECOM LIMITED 发明人 TURUDIC, ANDY
分类号 G01R31/28;(IPC1-7):G01R31/28 主分类号 G01R31/28
代理机构 代理人
主权项
地址