| 摘要 |
An integrated, user-programmable interconnect architecture, includes a plurality of input/output pads arranged in a matrix of rows and columns, each of the input/output pads being connected to a first one of its row neighbors and a first one of its column neighbors by a two-state programmable interconnect element in series with a first three-state programmable interconnect element having first programming characteristics. A plurality of first conductors is generally disposed in a direction parallel to the rows, each of the rows having at least one of the first conductors connected through ones of the first three-state programmable interconnect elements to selected ones of the input/output pads associated therewith, at least one of the first conductors segmented by at least one of the two-state programmable interconnect elements. A plurality of second conductors is generally disposed in a direction parallel to the columns, each of the columns having at least one of the second conductors connected through ones of the first three-state programmable interconnect elements to selected ones of the input/output pads associated therewith. The second conductors form intersections with the first conductors, and at least one of the second conductors is segmented by at least one two-state programmable interconnect element located at a selected position along its length. Ones of the first conductors and ones of the second conductors are connected together at selected intersections by ones of second three-state programmable interconnect elements having second programming characteristics.
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