| 摘要 |
PURPOSE:To evade confliction with buffer memory and to shorten the exclusive time of a common bus in an inter-processor data transfer system. CONSTITUTION:A BCTL 3 in a processor module 100 performs data transfer via the common bus 7. An SRCTR 12 supplies a write address to an SBUF 10, and an SWCTR 13 supplies a readout address to the SBUF 10, and an RWCTR 17 supplies the write address to an RBUF 15, and a PRCTR 18 supplies the readout address to the RBUF 15. Similarly. a BCTL 53 in a processor module 101 performs the data transfer via the common bus 7. An SRCTR 92 supplies the write address to an SBUF 90, and an SWCTR 93 supplies the readout address to the SBUF 90, and an RWCTR 97 supplies the write address to an RBUF 95, and a PRCTR 98 supplies the readout address to the RBUF 95. |
