INSTRUCTION DECODER USED AT INSIDE OF PROCESSOR, INSTRUCTION-ISSUANCE MECHANISM AND MICROPROCESSOR

摘要

PURPOSE: To provide a superscalar microprocessor with which operations can be executed by plural instructions on fetch, decode, execution and write-back stages. CONSTITUTION: This processor is provided with issue configuration equipped with an instruction cache 16 for fetching an instruction block containing plural instructions and an instruction decoder 18 for decoding and issuing the instructions to a functional unit for execution. The instruction decoder 18 applies an issue reference containing the conditions that the instructions are to be successively executed in the manner of inference, an operand for supporting the execution of instruction or a value added with a tag to be made usable later in place of that operand is to be usable and the functional unit required for executing the instructions is to be usable to the selected instructions in the respective instruction blocks, and the selected instructions satisfying these conditions are issued. The operations of the instruction decoder 18 and the instruction cache 16 are regulated by protocols, and the successive issue of instructions in ascending order and the efficient fetch of instruction blocks are made sure.