HIGH SPEED DATA PROCESSOR

摘要

a first logic controller for receiving a memory read signal and an address bus signal and generating respective control signals; a data storage and detector for receiving the control signals from the first logic controller and storing and detecting digital data; a second logic controller for receiving a memory write signal and an address bus signal and generating respective control signals; and first and second buffers for controlling a data bus transmitted from one of devices constituting the data storage and detector by the first and second logic controllers. The circuit reduces data transmission time.