Digital television signal processing circuit

摘要

The circuit includes an addressable memory (40) storing the signals, and a circuit (10) counting the number of bits corresp. to each type of data ordered in a partic. hierarchy. An allocation circuit (20) deals with each section of the image, and a number of bits is transmitted in channels of high and low priority.A control and redistribution circuit processes the data in packets of given length. The numbers of bits resulting from the allocations, and their average lengths are supplied to an addressable memory for reading from one part of it conforming to the redistribution process by data packets comprising blocks of equal length to the average bit lengths. The redistribution process allows placement of first bits indicating the hierarchical level in each packet. The surplus bits of one or other of the blocks remain in the complementary available place for the same type of data.