发明名称 SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To improve yield by replacing a redudant memory cell array with the other memory cell array when the redundant memory cell array replaced at the time of redundance relieving is defective. CONSTITUTION:This device is provided with a defective address memory circuit 1 which stores a defective address and generates a signal selecting a redundant memory cell array 7 at the time of selecting a defective address and generates a signal 3 selecting a regular memory cell array 6 at the time of selecting a normal address, a memory circuit 2 which controls so that the redundant memory cell array 7 relating to the defective address memory circuit 1 can not be selected independently of the fact whether an address externally given coincides with an address stored in the defective address memory circuit 1 or not.</p>
申请公布号 JPH06139796(A) 申请公布日期 1994.05.20
申请号 JP19920283376 申请日期 1992.10.22
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUURA TAKETOSHI
分类号 G11C11/413;G11C17/00;G11C29/00;G11C29/04;(IPC1-7):G11C29/00 主分类号 G11C11/413
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