发明名称 Method and Apparatus for Verifying Data Processing Apparatus
摘要 Asynchronous computation commands sent from a command control are held in a command queue. The executable command is selected and supplied to a pipelined asynchronous computing unit. A status area is ensured for every command held in the command queue and pipeline bits indicative of the state of progress of the execution of the command in the unit are stored. A queue verifier discriminates the pipeline bits and verifies that a plurality of pipeline stages do not exist in an entry of any single command and that a plurality of pipeline stages do not exist among the commands, thereby guaranteeing the correct and orderly execution of the commands. <IMAGE>
申请公布号 CA2105113(A1) 申请公布日期 1994.05.19
申请号 CA19932105113 申请日期 1993.08.30
申请人 FUJITSU LIMITED 发明人 NABEKURA, HIDEAKI;FUJIOKA, SHUNTARO
分类号 G06F9/38;G06F11/00;G06F11/08;(IPC1-7):G06F15/16 主分类号 G06F9/38
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