| 摘要 |
A signal line (28) runs in parallel with first to fourth bit lines (BL1, BL1, BL2, and BL2) on a memory cell array of a dynamic memory device. The signal line (28) runs between and along the first and third bit lines (BL1 and BL2), turns at a predetermined position, turns again and runs between and along the second and fourth bit lines (BL1 and BL2). The predetermined turning position is a position corresponding to the half of the bit line length. The result is that the stray capacitances between the signal line (28) and these bit lines (BL1, BL1, BL2, and BL2) are equal at about 1/2CF. |
