Interface circuit for controlling data transfers.

摘要

To provide an interface circuit which performs data transfer surely without a wasteful waiting time with the same hardware, whether the status reading by a host is performed before or after the data transfer. The interface circuit comprises interrupt means (60) for generating an interrupt request (IRQ) to a host (12) in response to a data request (DRQ) from a peripheral device (HDD) and dropping the interrupt request if the status of the peripheral device is read by the host, mode detecting means (62) for detecting that the host operates in a post-read mode, and interrupt enable means (64) responsive to the post-read mode detect signal from the mode detecting means and the status reading by the host to enable the interrupt means to regenerate the interrupt request to the host. <IMAGE>