发明名称 Co-processor de-coupling bus structure
摘要 A special type of random access memory referred to as video random access memory (VRAM) is used through to provide multiple access to the memory in a timely manner. The VRAM is characterized by a random access port which enables random accessing to the memory array and a serial port comprising a shift register for outputting a large group of bits of data, such as pixels representative of a scan line of a video image, which are rapidly output by the memory. In the present invention, the VRAM is utilized in a different manner to provide more efficient use of memory without degradation in system performance. The VRAM provides for communications between processors as well as the memory utilized by the coprocessor for storage of code and data. Communications between processors is performed through the serial port; therefore, data is communicated via blocks of data transfers minimizing the frequency of access to the memory array. The co-processor, which utilizes the memory for processing and code storage, communicates with the memory through the random access port in order for the co-processor to perform its functions in a timely manner. The co-processor will only be interrupted in its access of the memory when it is determined that blocks of data are to be transferred into the or out of the memory via the serial port.
申请公布号 US5313586(A) 申请公布日期 1994.05.17
申请号 US19920847190 申请日期 1992.03.06
申请人 INTEL CORPORATION 发明人 RUTMAN, SERGE
分类号 G06F9/38;G06F13/42;(IPC1-7):G06F13/00 主分类号 G06F9/38
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