发明名称 |
Synchronous static random access memory |
摘要 |
Maximum operating speed is achieved in an array of memory cells by performing both read and write operations within a single memory cycle. As outgoing data are read from the memory cells, incoming data are stored immediately in those cells. Once data are read from the memory cells, a latch signal is generated to trigger latching of the read data for output to a data bus. The same latch signal that is used to latch the read data initiates the writing of new data to the memory cells. Use of a single latch signal in this manner ensures that new data are not written to the memory cells until the existing data has been read from those cells.
|
申请公布号 |
US5309395(A) |
申请公布日期 |
1994.05.03 |
申请号 |
US19920965127 |
申请日期 |
1992.10.22 |
申请人 |
AT&T BELL LABORATORIES |
发明人 |
DICKINSON, ALEXANDER G.;HATAMIAN, MEHDI;RAO, SAILESH K. |
分类号 |
G11C11/413;G11C11/417;G11C11/419;H04L12/56;H04Q11/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/413 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|