| 摘要 |
Lock apparatus for a dual PLL which is capable of detecting a locked state of a receiving frequency as well as a locked state of a transmitting frequency. The dual PLL lock apparatus comprises a receive lock detector for detecting the phase locked state of the receiving frequency in response to a locked state signal from a receiving phase difference detector, in addition to the conventional dual PLL lock apparatus which can lock the transmitting and receiving frequencies, respectively, and detect the locked state of the transmitting frequency. The receive lock detector comprises a reset signal generating circuit for generating a reset signal in response to the receive locked state signal from the receiving phase difference detector, a frequency-dividing circuit for dividing a predetermined frequency from the reference frequency counter by a given ratio in response to the reset signal from the reset signal generating circuit, and a receive lock data output circuit for outputting receive lock data in response to an output signal from the frequency-dividing circuit.
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