MEMORY-QUEUE IN A SYSTEM USING PIPE-LINE BUS PROTOCOL

摘要

The memory queue for pipeline bus protocol system as a buffer between the memory controller and the bus interface to store bus transmission request temporarily to send to the memory controller in time for efficient memory access. The memory queue comprises a memory array (10) for storing data, a memory controller (20) to control the memory array (10) which is connected to bus interface (40), and a buffer (30) which stores continuous transmission requests from the system bus, when the memory controller (20) can not process those requests, to transmit to the memory controller (20) when the memory controller (20) is ready.