发明名称 SUBSTRATE BIAS CIRCUIT OF MOS INTEGRATED CIRCUIT
摘要 PURPOSE:To vary the substrate bias according to the output voltage of the inverter by controlling the level of clamp potential through selective connection to the feedback path with application of a bootstrap type feedback to FET under the load of an E (enhancement) type MOS inverter. CONSTITUTION:The output of a generator 1 drives an E-type inverter 2 employing a MOSFET Q7/Q8. When the output is VH, a MOSFET Q11 is turned on, and D (depletion) type MOSFET Q10 is charged so that the potential of the contact e reaches -VH at OV. Therefore, if the threshold of the E-type MOSFET is VTH, the output VTH-VH develops at the terminal f. When the gate input of the D-type MOSFET Q9 is OV while the output terminal c is at OV, the potential of a contact d on the D-type MOSFET Q13 (capacity) reaches 2VDD-VTH. Thus, the potential VTH-VDD develops at the terminal f. When a high level input is applied to the gate a, the FET Q9 is turned on and the contact d is clamped at a potential VDD. Only the output VDD-VTH develops at the output terminal, leading the output of the terminal f to be 2VTH-VDD. In this manner, the power consumption and the working speed can be switched by changing the bias of the substrate.
申请公布号 JPS5587470(A) 申请公布日期 1980.07.02
申请号 JP19780160431 申请日期 1978.12.25
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KANUMA AKIYOSHI
分类号 H01L27/04;G05F3/20;G11C11/407;H01L21/822;H01L29/78 主分类号 H01L27/04
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