| 摘要 |
An interfacing controller (20) is disclosed for use in a host computer system (Fig 1, not shown). A buffer memory circuit (22) is used for storage of all incoming data blocks received at ports (21). A foreground monitor circuit (23) attempts to decode data blocks to identify addressee nodes which have the greatest likelihood of receiving a message, at regular intervals determined by a clock circuit (29). This is carried out with reference to a stored file containing the addresses of "likely" addressee nodes. A background monitor circuit (30) attempts to decode identified by the foreground monitor circuit (23). This data blocks which have not been successfully is carried out with reference to a "comprehensive" addressee file (32). An indication is provided if neither circuit identifies an addressee node for the received data. Both circuits are constructed to transmit the data block to an identified addressee node (35, 27) in parallel with transmission to an updating record (36, 28). <IMAGE>
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