Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring

摘要

When a pre-shipment test of a SRAM is requested, a pulse signal PL having a pulse width exceeding a predetermined time length is applied through a terminal 62. A pulse width detecting circuit 80 detects the pulse width of the applied pulse signal to provide a holding signal HD. A test mode signal holding circuit 90 holds an externally applied test mode request signal TM' in response to the holding signal HD. After the completion of the pre-shipment test, pulse width detecting circuit 80 is disabled by a fusion of a fuse 71. Fuse 71 is fused after the pre-shipment test is conducted, whereby the test mode operation is prevented from undesirably occurring.