| 摘要 |
A data path aligner transfers data from an input having N byte lanes with byte enable bits to an output having N byte lanes. The aligner includes first stage having N-1 selector/registers, and a second stage having N selector/registers. Each of the N-1 selector/registers S1(i) in the first stage has inputs including input lanes L(j) for j going from i+1 to N. Each of the selector/registers S2(i) in the second stage has inputs including input lanes L(k) for k going from i to 0, and for selector/registers S2(i) for i less than or equal to N-2, the inputs include the output of a first stage selector/register S1(i). The outputs of the second stage selector/registers supply data selected from the respective inputs to output segment lanes. All of these selector/registers are controlled by a common select signal derived from a data path offset, and all selector/registers are clocked by a common clock. |
