发明名称 STATE CHANGE MONITOR SYSTEM
摘要 PURPOSE:To reduce the burden to a CPU and to dispense with the increase if wirings and registers for monitor and control even at the time of the increase of the number of monitor and control object units. CONSTITUTION:Each of transmission/reception units 1-1 to 1-n is provided with a transmission/reception control part 11 which adds new and old state information and state change/non-change information to main data to send them to a bus 5. An interface part 3 is provided with a 2-port RAM 32 where new and old state information are stored together with main data received from each unit, a state change detector 33 which detects state change/non-change information in data to output a state change detection pulse, a unit number output part 35 which outputs the number of the transmission unit from which data is received at present, and a unit number register 34 which holds the number of the unit of the state change to report it to a CPU 4 at the timing of the state change detection pulse. The CPU 4 recognizes this unit and detects the item of the state change by new and old state information in the corresponding address of the 2-port RAM 32.
申请公布号 JPH0697864(A) 申请公布日期 1994.04.08
申请号 JP19920245332 申请日期 1992.09.16
申请人 FUJITSU LTD 发明人 IGARASHI HIRONOBU
分类号 H04B7/26;H04B17/00 主分类号 H04B7/26
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