| 摘要 |
<p>A BICMOS level converter (60) for use at lower power supply voltages includes an input buffer (20) for receiving an ECL level input signal and providing level shifted buffered signals referenced to VSS, a differential amplifier (61), a clamping circuit (71 and 72) for preventing the bipolar transistors (64 and 65) from operating in saturation, cross-coupled pull-up circuit (67) for a stronger transition from a logic low to a logic high, and a cross-coupled half-latch (75) for reducing the power consumption. The BICMOS level converter (60) has improved switching speeds, wider margins, and reduced power consumption for use at 3.3 volts. <IMAGE></p> |
