| 摘要 |
A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a field programmable logic array (FPLA) using a dedicated product term for macrocell control. Particularly, the macrocells contain a faster, more flexible, and exclusive feedback line as well as an exclusive external-input line from an input/output (I/O) pad for a registered mode of operation. Moreover, there is a registered mode macrocell which has 1) a feedback path for the registered mode signals which is activated even when the I/O pad driver is disabled, 2) an input path, to the logic circuitry, over an I/O pad, 3) a feedback path for the registered mode signals while outputting the same registered mode signals, and 4) a feedback path which avoids the unnecessary signal noise emanating from the use of a 3-state device or output driver. In addition, the macrocell allows for a disabled tri-state and still have the feedback intact for the combinatorial mode; thus, avoiding the extra noise that a tri-state creates.
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