发明名称 Video white signal compression and peaking
摘要 A video white compression and peaking arrangement comprises a plurality of inverting amplifier transistors each tied to a common threshold level. RGB input video signals are applied to the inverting amplifier transistors which are ineffective for signals below the threshold level. The transistors are progressively turned on for input signals that exceed the threshold level resulting in non-linear negative feedback signals that compress the output signals by subtraction. A tuned circuit is coupled across the input of each inverting amplifier transistor for bypassing selected frequencies from the negative feedback effect and relatively peaking those frequencies in the output signal.
申请公布号 US5299000(A) 申请公布日期 1994.03.29
申请号 US19920900204 申请日期 1992.06.17
申请人 ZENITH ELECTRONICS CORP. 发明人 SRIVASTAVA, GOPAL K.
分类号 H04N9/64;H04N9/68;(IPC1-7):H04N5/20;H04N5/14 主分类号 H04N9/64
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