发明名称 Process for forming implanted regions with lowered channeling risk on semiconductors.
摘要 <p>A process for forming implanted regions with lowered channelling risk on semiconductors, wherein the semiconductor devices include at least one layer of polycrystalline silicon which covers all isolation regions and active areas which are liable to a channelling phenomena and wherein the process includes masking the areas or regions to be implanted on the polycrystalline layer, implanting a first dopant species having a high atomic weight to amorphousize the polycrystalline silicon in any unmasked areas, removing the masking layer, and implanting a second dopant species over the entire semiconductor. &lt;IMAGE&gt;</p>
申请公布号 EP0588032(A2) 申请公布日期 1994.03.23
申请号 EP19930111968 申请日期 1993.07.27
申请人 SGS-THOMSON MICROELECTRONICS S.R.L. 发明人 ZACCHERINI, CHIARA
分类号 H01L21/8244;H01L21/265;H01L21/02;H01L21/3215;H01L27/11;(IPC1-7):H01L21/265;H01L21/321 主分类号 H01L21/8244
代理机构 代理人
主权项
地址